Integrated circuit (IC) packages typically include a semiconductor die (e.g., a silicon semiconductor chip) that is suitably protected. Generally, the semiconductor die includes a plurality of electrically-conductive (e.g., metal) pads for transmitting and receiving signals, supply voltages, and electrical, optical or other input parameters to and from one or more external devices. Typically, these die pads are electrically or otherwise coupled to respective pins attached to the external portion of the IC package. Usually, a complex interconnection is employed to route (e.g., fan-out and/or fan-in) the electrical connection from the semiconductor die pads to the respective pins, as exemplified below.
FIG. 1 illustrates a side sectional view of an exemplary integrated circuit (IC) package 100. The IC package 100 includes a housing consisting of a substrate 102 serving as a base of the housing, and a cover 108 mechanically or adhesively coupled to the substrate 102 in a manner to form an enclosure. Although, in this example, the cover 108 is a solid piece formed by a molding material over the substrate 102, protection covers for IC package may take on many distinct forms. The IC package 100 further includes one or more semiconductor dies 110 situated within the enclosure, and disposed on an upper surface of the substrate 102. Other surface mount components such as resistors, capacitors, inductors, etc. may also co-exist within or on the IC package 100.
The semiconductor die 110 includes on its upper surface a plurality of contact pads 112. The substrate 102 includes on its lower and external surface a plurality of contact pins 106. In this example, the plurality of pins is configured as a ball grid array (BGA). However, other types of pin configurations are used, such as land grid array (LGA), pin-grid array, etc. The substrate 102 also typically includes metalized traces and via-holes to route the interconnection from within the enclosure to the external pins 106.
Because the pitch P1 (lateral distance between adjacent pads) of the contact pads 112 is typically different than the pitch P2 (lateral distance between adjacent pins) of the external pins 106, the substrate 102 further serves as a multi-layer interconnect for fanning out the electrical connections from the contact pads 112 to the external pins 106. The contact pads 112 of the semiconductor die 110 are electrically, optically or otherwise coupled to the multi-layer interconnect of the substrate 102 via a plurality of wirebonds 116. The multi-layer interconnect of the substrate 102 is electrically coupled to the external pins 106 by means of metalized via-holes and metal traces as illustrated.
There are several drawbacks with this IC package configuration. First, although the substrate 102 helps with fan-out and fan-in, the size, complexity and hence cost of the package is limited by the line/space capabilities of the substrate fabrication process, pitch and the number of interconnects on the die 110 and on the IC package 100. Typically, many routing layers are required to connect all the pins 112 on the die 110 to the corresponding pins 106 of the package 100, while simultaneously keeping the package size relatively small. Complex routing schemes on the substrate 102 increases its cost and generally increases the reliability risk of the IC package 100. Current carrying capacity of the IC package 100 could also be limited, and due to parasitic capacitance and inductance thereof, the frequency of the signals processed by the IC package may likewise be limited.
FIG. 2A illustrates a side sectional view of another exemplary integrated circuit (IC) package 200. The IC package 200 is similar to the previously-discussed IC package 100, and includes the same or similar elements as noted b the same reference numbers with a most significant digit as a “2” instead of a “1.” For example, the IC package 200 includes contact pins 206 and cover 208. The IC package 200 differs from package 100 in that it is in a flip-chip configuration. That is, the semiconductor die 210 is flipped p-side-down such that its contact pads 212 are facing towards the substrate 202. In this configuration, the contact pads 212 make direct connection to the multi-layered interconnect of the substrate 202. Although the flip-chip configuration eliminates the wirebonds of the previous IC package 100, it still experiences challenges similar to those for the wirebond package configuration previously discussed.
FIG. 2B illustrates a side sectional view of yet another exemplary integrated circuit (IC) package 250. The IC package 250 is similar to the previously-discussed IC package 200, and includes the same or similar elements as noted by the same reference numbers. The IC package 250 differs from package 200 in that the contacts 220 of the semiconductor die 210 are configured as miniature balls, typically made from solder or other suitable conductive materials, instead of flat contact pads 212. Nonetheless, the IC package 250 still experiences challenges similar to those previously discussed with reference to IC package 100.